For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
Non-volatile semiconductor memories typically use stacked floating gate type field-effect-transistors. In such transistors, electrons are injected into a floating gate of a memory cell to be programmed by biasing a control gate and grounding a body region of a substrate on which the memory cell is formed. An oxide-nitride-oxide (ONO) stack is used as either a charge storing layer, as in a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) transistor, or as an isolation layer between the floating gate and control gate, as in a split gate flash transistor. FIG. 1 illustrates a cross-sectional view of a conventional nonvolatile charge trap memory device.
Referring to FIG. 1, semiconductor device 100 includes a SONOS gate stack 104 including a conventional ONO portion 106 formed over a silicon substrate 102. Semiconductor device 100 further includes source and drain regions 110 on either side of SONOS gate stack 104 to define a channel region 112. SONOS gate stack 104 includes a poly-silicon gate layer 108 formed above and in contact with ONO portion 106. Poly-silicon gate layer 108 is electrically isolated from silicon substrate 102 by ONO portion 106. ONO portion 106 typically includes a tunnel oxide layer 106A, a nitride or oxy-nitride charge-trapping layer 106B, and a top oxide layer 106C overlying nitride or oxy-nitride layer 106B.
One problem with conventional SONOS transistors is the limited program and erase window achievable with a conventional blocking layer 106C, inhibiting optimization of semiconductor device 100. For example, FIG. 2 is a plot 200 of Threshold Voltage (V) as a function of Pulse Width (s) in erase mode for a conventional nonvolatile charge trap memory device. Referring to FIG. 2, line 202 is a measure of decreasing threshold voltage (in Volts) as a function of time (in seconds) in response to an erase-mode voltage being applied to a gate electrode in a conventional SONOS transistor. As indicated by region 204 of line 202, the ability of the erase mode to decrease the threshold voltage of the gate electrode saturates with time, restricting an erase event to a relatively shallow erase of the gate electrode. The shallow erase limits the differential between erase and program modes for a SONOS-transistor and thus limits the performance of such a device.